1. Technical Field
The present invention relates to integrated circuits (ICs) with AC coupling on the I/O pins, where DC balance is desired for at least some data signals provided to the I/O pins. More particularly, the present invention relates to providing a bypass to the AC coupling to enable DC balance of an input data signal.
2. Related Art
AC-coupling is desirable for a number of reasons—(1) To change the DC bias level when interconnecting logic families with different switching thresholds; (2) To provide a removable interface that may be shorted to ground without damaging the output drivers; or (3) When combined with differential signaling and transformer coupling, to connect boxes without requiring any DC connection between the two product chassis.
AC coupling is typically accomplished using a high-pass filter placed in series with a transmission line. A series-connected DC-blocking capacitor is a good example of a commonly used high-pass filter. The DC-blocking capacitor strips away all low-frequency content in the signal. If a signal has good DC balance, it is possible to pass it through a suitable high-pass filter without altering the informational content. If the signal is not DC balanced, AC coupling is typically undesirable.
For a signal to be DC balanced, one property of the signal is that it has a substantially equal numbers of ones and zeros. The DC balanced signal will have a median voltage level fixed, typically at zero volts. A DC offset can be created by a significantly unequal number of ones and zeros. The DC offset can also be created with a long dead time in a signal stream allowing charge to build up on the transmission line carrying the signal.
Because only AC signals that have good DC balance are anticipated as input signals, some IC manufacturers have included AC coupling on the I/O pins. One example of an IC with AC coupling capacitors placed in the chips connected to its I/O pins is the Virtex-II PRO X FPGA manufactured by Xilinx, Inc. of San Jose, Calif.
A new problem has therefore been created when devices with integrated AC coupling capacitors on I/O pins are targeted for applications that do not meet DC balance/run length criteria, or for input signals with unknown characteristics. For example, the Virtex-II Pro X FPGA uses Multi-Gigabit Transceivers (MGTs) as high speed over-sampling and/or digitizing engines for input data streams. For some input data streams long dead periods, or completely unknown DC characteristics creating bad DC balance, so some form of DC coupling is needed at the input of the MGTs to provide DC balance correction for error free data to be received. AC coupling is, thus, undesirable for such input data streams.
For applications using ICs with integrated AC coupling capacitors, a method for defeating the AC coupling is thus desirable in order to simulate an interface with DC coupling characteristics. One solution is for manufacturers to provide a switch to bypass the AC coupling capacitor when signals are expected where AC coupling is undesirable. However, if the manufacturer does not provide bypass switches it is desirable to provide an alternative approach to bypass or defeat the AC coupling.